synchronizer.vhd

--------------------------------------------------------------------------

-- FILENAME : synchronizer.vhd

--

-- Synchronize the UNSYNC_IN signal with the CLK to reduce metastability.

--

-- AUTHOR       : Craig Dunn

-- DATE STARTED : 8 December 2003

-- TAB SETTING  : 4

-- CLEAR        : Async (active low)

-- KNOWN BUGS   : None

-- VERSION      : 1.0

--

-- All of the design and code in this module is my own work.  No design or

-- code has been borrowed or copied from any source.

--------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;



entity synchronizer is

   port( CLK         : in std_logic;

         CLR         : in std_logic;

         UNSYNC_IN   : in std_logic;

         SYNC_OUT    : out std_logic

       );

end synchronizer;



architecture synchronizer_arch of synchronizer is



   component flipflop

   port( D     : in  std_logic;

         CLK   : in  std_logic;          

         CLR   : in  std_logic;

         Q     : out std_logic

      );

   end component;



   signal wire : std_logic;



begin



   ff1 : flipflop port map ( 

      D     => UNSYNC_IN,

      CLK   => CLK,

      CLR   => CLR,

      Q     => wire

   );



   ff2 : flipflop port map ( 

      D     => wire,

      CLK   => CLK,

      CLR   => CLR,

      Q     => SYNC_OUT

   );



end architecture synchronizer_arch;