*

step_controller.vhd


--------------------------------------------------------------------------

-- FILENAME : step_controller.vhd
--
-- This component is responsible for moving the read / write head to the
-- correct track during normal operations. When the init_controller
-- component is active it has total control of the read / write head and
-- this component synchronusly resets.
--
-- AUTHOR : Craig Dunn
-- DATE STARTED : 30 December 2003
-- TAB SETTING : 4
-- CLEAR : Sync (controller_rdy)
-- KNOWN BUGS : None
-- VERSION : 1.0
--
-- All of the design and code in this module is my own work. No design or
-- code has been borrowed or copied from any source.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity step_controller is
port ( RST : in std_logic;
MCLK : in std_logic;
EN : in std_logic;
TRACK : in std_logic_vector(7 downto 0);
BSY : out std_logic;
STEP : out std_logic;
DIRECTION : out std_logic
);
end step_controller;

architecture step_controller_arch of step_controller is

signal move_head : std_logic;
signal current_track : std_logic_vector(7 downto 0);
signal step_dly : integer range 0 to 200000;

constant DURATION_5MS : integer := 160000;
constant DURATION_4MS : integer := 128000;
begin

DIRECTION <= '1' when current_track > TRACK else '0';
BSY <= '0' when (current_track = TRACK and step_dly = 0) else '1';
STEP <= '0' when step_dly >= DURATION_4MS else '1';

main : process(RST, MCLK)
begin
if RST = '0' then
current_track <= (others => '0');
step_dly <= 0;
move_head <= '0';
elsif rising_edge(MCLK) then
if EN = '0' then
move_head <= '0';
step_dly <= 0;
elsif move_head = '1' then
if step_dly = DURATION_5MS then
move_head <= '0';
step_dly <= 0;
else
step_dly <= step_dly + 1;
end if;
elsif current_track < TRACK then
current_track <= current_track + 1;
move_head <= '1';
elsif current_track > TRACK then
current_track <= current_track 1;
move_head <= '1';
end if;
end if;
end process main;

end step_controller_arch;


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