shift_32.vhd

--------------------------------------------------------------------------

-- FILENAME : shift_32.vhd

--

-- A 32 bit shift register for holding the basic mfm signal.

--

-- AUTHOR       : Craig Dunn

-- DATE STARTED : 20 December 2003

-- TAB SETTING  : 4

-- RESET        : Async

-- CLOCK        : DPLL_CLK

-- KNOWN BUGS   : None

-- VERSION      : 1.0

--

-- All of the design and code in this module is my own work.  No design or

-- code has been borrowed or copied from any source.

--------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;



entity shift_32 is

    port ( RST       : in std_logic;

           CLK       : in std_logic;

           D         : in std_logic;

           Q         : out std_logic_vector(31 downto 0)

         );

end shift_32;



architecture shift_32_arch of shift_32 is

   signal data : std_logic_vector(31 downto 0);

begin



   Q <= data;



   main : process(RST, CLK)

   begin

      if RST = '0' then

         data <= (others => '0');

      elsif rising_edge(CLK) then

         data <= data(30 downto 0) & d;

      end if;

   end process main;



end shift_32_arch;