 | idc_top.vhd
--------------------------------------------------------------------------
-- FILENAME : idc_top.vhd
--
-- The top level file of the system. See the individual components for
-- descriptions.
--
-- AUTHOR : Craig Dunn
-- DATE STARTED : 10 April 2004
-- TAB SETTING : 4
-- RESET : Async (active low)
-- CLOCK : 32MHz (clock dependent)
-- KNOWN BUGS : None
-- VERSION : 1.0
--
-- All of the design and code in this module is my own work. No design or
-- code has been borrowed or copied from any source.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity idc_top is
port ( RST : in std_logic;
MCLK : in std_logic;
TRACK_00 : in std_logic;
INDEX : in std_logic;
READ_DATA : in std_logic;
WRITE_PROTECT : in std_logic;
DISK_CHANGE : in std_logic;
I2C_ADDR : in std_logic_vector(2 downto 0);
DRIVE_SELECT : out std_logic;
MOTOR_ON : out std_logic;
DIRECTION_SELECT : out std_logic;
STEP : out std_logic;
WRITE_GATE : out std_logic;
WRITE_DATA : out std_logic;
SIDE_ONE_SELECT : out std_logic;
SDA : inout std_logic;
SCL : inout std_logic
);
end idc_top;
architecture idc_top_arch of idc_top is
component fddcontroller
port(
RST : in std_logic;
MCLK : in std_logic;
TRACK_00 : in std_logic;
INDEX : in std_logic;
READ_DATA : in std_logic;
WRITE_PROTECT : in std_logic;
DISK_CHANGE : in std_logic;
RD_SECT : in std_logic;
WR_SECT : in std_logic;
MEM_CLK : in std_logic;
MEM_WE : in std_logic;
SECTOR : in std_logic_vector(4 downto 0);
TRACK : in std_logic_vector(7 downto 0);
SIDE : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ADDR : in std_logic_vector(8 downto 0);
DRIVE_SELECT : out std_logic;
MOTOR_ON : out std_logic;
DIRECTION_SELECT : out std_logic;
STEP : out std_logic;
WRITE_GATE : out std_logic;
WRITE_DATA : out std_logic;
SIDE_ONE_SELECT : out std_logic;
RDY : out std_logic;
BSY : out std_logic;
CRC_ERROR : out std_logic;
SEEK_ERROR : out std_logic;
WP_ERROR : out std_logic;
DATA_OUT : out std_logic_vector(7 downto 0)
);
end component;
component rw_byte
port(
MCLK : in std_logic;
SIDE_IN : in std_logic;
RD_BYTE : in std_logic;
WR_BYTE : in std_logic;
FDD_BSY : in std_logic;
FDD_RDY : in std_logic;
CRC_ERROR : in std_logic;
SEEK_ERROR : in std_logic;
WP_ERROR : in std_logic;
SECTOR_IN : in std_logic_vector(4 downto 0);
TRACK_IN : in std_logic_vector(7 downto 0);
RAM_DO : in std_logic_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
ADDR_IN : in std_logic_vector(8 downto 0);
SIDE_OUT : out std_logic;
BSY : out std_logic;
ERROR : out std_logic;
RAM_CLK : out std_logic;
RAM_WE : out std_logic;
RD_SECT : out std_logic;
WR_SECT : out std_logic;
SECTOR_OUT : out std_logic_vector(4 downto 0);
RAM_DI : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
TRACK_OUT : out std_logic_vector(7 downto 0);
ADDR_OUT : out std_logic_vector(8 downto 0)
);
end component;
component read_fat
port(
EN : in std_logic;
MCLK : in std_logic;
ENTRY : in std_logic_vector(11 downto 0);
RD : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
RW_BSY : in std_logic;
BSY : out std_logic;
FAT_OUT : out std_logic_vector(11 downto 0);
RAM_ADDR : out std_logic_vector(8 downto 0);
SECTOR : out std_logic_vector(4 downto 0);
SIDE : out std_logic;
TRACK : out std_logic_vector(7 downto 0);
RD_BYTE : out std_logic
);
end component;
component write_fat
port(
EN : in std_logic;
MCLK : in std_logic;
WR : in std_logic;
RW_BSY : in std_logic;
DATA_IN : in std_logic_vector(7 downto 0);
ENTRY : in std_logic_vector(11 downto 0);
FAT_VALUE : in std_logic_vector(11 downto 0);
RD_BYTE : out std_logic;
WR_BYTE : out std_logic;
SIDE : out std_logic;
BSY : out std_logic;
SECTOR : out std_logic_vector(4 downto 0);
TRACK : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
RAM_ADDR : out std_logic_vector(8 downto 0)
);
end component;
component i2c_manager
port(
RST : in std_logic;
MCLK : in std_logic;
RAM_DO : in std_logic_vector(7 downto 0);
RDY : in std_logic;
BSY : in std_logic;
CRC_ERROR : in std_logic;
SEEK_ERROR : in std_logic;
WP_ERROR : in std_logic;
FAT_VALUE_IN : in std_logic_vector(11 downto 0);
DIR_OFFSET : in std_logic_vector(8 downto 0);
I2C_ADDR : in std_logic_vector(2 downto 0);
SCL : inout std_logic;
SDA : inout std_logic;
TRACK : out std_logic_vector(7 downto 0);
SIDE : out std_logic;
WR_SECT : out std_logic;
RD_SECT : out std_logic;
SECTOR : out std_logic_vector(4 downto 0);
FAT_VALUE_OUT : out std_logic_vector(11 downto 0);
FAT_ENTRY : out std_logic_vector(11 downto 0);
DIR_ENTRY : out std_logic_vector(7 downto 0);
MEM_WE : out std_logic;
RAM_CLK : out std_logic;
RD_FAT : out std_logic;
WR_FAT : out std_logic;
SET_DIR : out std_logic;
WR_DIR : out std_logic;
RAM_DI : out std_logic_vector(7 downto 0);
MEM_ADDR : out std_logic_vector(8 downto 0)
);
end component;
component set_directory
port(
FDD_RDY : in std_logic;
MCLK : in std_logic;
FDD_BSY : in std_logic;
ENTRY : in std_logic_vector(7 downto 0);
SET : in std_logic;
WR_DIR : in std_logic;
RAM_WE : out std_logic;
SET_BSY : out std_logic;
TRACK : out std_logic_vector(7 downto 0);
SIDE : out std_logic;
SECTOR : out std_logic_vector(4 downto 0);
OFFSET : out std_logic_vector(8 downto 0);
WR_SECT : out std_logic;
RD_SECT : out std_logic
);
end component;
signal i2c_man_track : std_logic_vector(7 downto 0);
signal i2c_man_side : std_logic;
signal i2c_man_wr_sect : std_logic;
signal i2c_man_rd_sect : std_logic;
signal i2c_man_sector : std_logic_vector(4 downto 0);
signal i2c_man_fat_value_out : std_logic_vector(11 downto 0);
signal i2c_man_fat_entry : std_logic_vector(11 downto 0);
signal i2c_man_dir_entry : std_logic_vector(7 downto 0);
signal i2c_man_ram_we : std_logic;
signal i2c_man_wr_dir : std_logic;
signal i2c_man_ram_clk : std_logic;
signal i2c_man_ram_addr : std_logic_vector(8 downto 0);
signal i2c_man_ram_di : std_logic_vector(7 downto 0);
signal i2c_man_set_dir : std_logic;
signal wr_fat_wr : std_logic;
signal wr_fat_rd_byte : std_logic;
signal wr_fat_wr_byte : std_logic;
signal wr_fat_side : std_logic;
signal wr_fat_bsy : std_logic;
signal wr_fat_sector : std_logic_vector(4 downto 0);
signal wr_fat_track : std_logic_vector(7 downto 0);
signal wr_fat_ram_addr : std_logic_vector(8 downto 0);
signal rd_fat_bsy : std_logic;
signal rd_fat_rd : std_logic;
signal rd_fat_fat_out : std_logic_vector(11 downto 0);
signal rd_fat_ram_addr : std_logic_vector(8 downto 0);
signal rd_fat_sector : std_logic_vector(4 downto 0);
signal rd_fat_side : std_logic;
signal rd_fat_track : std_logic_vector(7 downto 0);
signal rd_fat_rd_byte : std_logic;
signal rw_byte_side_in : std_logic;
signal rw_byte_rd_byte : std_logic;
signal rw_byte_wr_byte : std_logic;
signal rw_byte_sector_in : std_logic_vector(4 downto 0);
signal rw_byte_track_in : std_logic_vector(7 downto 0);
signal rw_byte_data_in : std_logic_vector(7 downto 0);
signal rw_byte_addr_in : std_logic_vector(8 downto 0);
signal rw_byte_side_out : std_logic;
signal rw_byte_bsy : std_logic;
signal rw_byte_error : std_logic;
signal rw_byte_ram_clk : std_logic;
signal rw_byte_ram_we : std_logic;
signal rw_byte_rd_sect : std_logic;
signal rw_byte_wr_sect : std_logic;
signal rw_byte_sector_out : std_logic_vector(4 downto 0);
signal rw_byte_data_out : std_logic_vector(7 downto 0);
signal rw_byte_track_out : std_logic_vector(7 downto 0);
signal rw_byte_addr_out : std_logic_vector(8 downto 0);
signal rw_byte_ram_di : std_logic_vector(7 downto 0);
signal fdd_rd_sect : std_logic;
signal fdd_wr_sect : std_logic;
signal fdd_ram_clk : std_logic;
signal fdd_ram_we : std_logic;
signal fdd_sector : std_logic_vector(4 downto 0);
signal fdd_track : std_logic_vector(7 downto 0);
signal fdd_side : std_logic;
signal fdd_data_in : std_logic_vector(7 downto 0);
signal fdd_ram_addr : std_logic_vector(8 downto 0);
signal fdd_rdy : std_logic;
signal fdd_bsy : std_logic;
signal fdd_crc_error : std_logic;
signal fdd_seek_error : std_logic;
signal fdd_wp_error : std_logic;
signal fdd_data_out : std_logic_vector(7 downto 0);
signal sd_ram_we : std_logic;
signal sd_bsy : std_logic;
signal sd_track : std_logic_vector(7 downto 0);
signal sd_side : std_logic;
signal sd_sector : std_logic_vector(4 downto 0);
signal sd_offset : std_logic_vector(8 downto 0);
signal sd_rd_sect : std_logic;
signal sd_wr_sect : std_logic;
begin
c0 : fddcontroller port map(
RST => RST,
MCLK => MCLK,
TRACK_00 => TRACK_00,
INDEX => INDEX,
READ_DATA => READ_DATA,
WRITE_PROTECT => WRITE_PROTECT,
DISK_CHANGE => DISK_CHANGE,
DRIVE_SELECT => DRIVE_SELECT,
MOTOR_ON => MOTOR_ON,
DIRECTION_SELECT => DIRECTION_SELECT,
STEP => STEP,
WRITE_GATE => WRITE_GATE,
WRITE_DATA => WRITE_DATA,
SIDE_ONE_SELECT => SIDE_ONE_SELECT,
RD_SECT => fdd_rd_sect,
WR_SECT => fdd_wr_sect,
MEM_CLK => fdd_ram_clk,
MEM_WE => fdd_ram_we,
SECTOR => fdd_sector,
TRACK => fdd_track,
SIDE => fdd_side,
DATA_IN => fdd_data_in,
ADDR => fdd_ram_addr,
RDY => fdd_rdy,
BSY => fdd_bsy,
CRC_ERROR => fdd_crc_error,
SEEK_ERROR => fdd_seek_error,
WP_ERROR => fdd_wp_error,
DATA_OUT => fdd_data_out
);
fdd_ram_clk <= rw_byte_ram_clk or i2c_man_ram_clk;
fdd_side <= rw_byte_side_out when rw_byte_bsy = '1' else sd_side when sd_bsy = '1' else i2c_man_side;
fdd_track <= rw_byte_track_out when rw_byte_bsy = '1' else sd_track when sd_bsy = '1' else i2c_man_track;
fdd_sector <= rw_byte_sector_out when rw_byte_bsy = '1' else sd_sector when sd_bsy = '1' else i2c_man_sector;
fdd_ram_we <= rw_byte_ram_we when rw_byte_bsy = '1' else sd_ram_we when sd_bsy = '1' else i2c_man_ram_we;
fdd_ram_addr <= rw_byte_addr_out when rw_byte_bsy = '1' else i2c_man_ram_addr;
fdd_data_in <= rw_byte_ram_di when rw_byte_bsy = '1' else i2c_man_ram_di;
fdd_rd_sect <= rw_byte_rd_sect when rw_byte_bsy = '1' else sd_rd_sect when sd_bsy = '1' else i2c_man_rd_sect;
fdd_wr_sect <= rw_byte_wr_sect when rw_byte_bsy = '1' else sd_wr_sect when sd_bsy = '1' else i2c_man_wr_sect;
c1 : rw_byte port map(
MCLK => MCLK,
SIDE_IN => rw_byte_side_in,
RD_BYTE => rw_byte_rd_byte,
WR_BYTE => rw_byte_wr_byte,
FDD_BSY => fdd_bsy,
FDD_RDY => fdd_rdy,
CRC_ERROR => fdd_crc_error,
SEEK_ERROR => fdd_seek_error,
WP_ERROR => fdd_wp_error,
SECTOR_IN => rw_byte_sector_in,
TRACK_IN => rw_byte_track_in,
RAM_DO => fdd_data_out,
DATA_IN => rw_byte_data_in,
ADDR_IN => rw_byte_addr_in,
SIDE_OUT => rw_byte_side_out,
BSY => rw_byte_bsy,
ERROR => rw_byte_error,
RAM_CLK => rw_byte_ram_clk,
RAM_WE => rw_byte_ram_we,
RD_SECT => rw_byte_rd_sect,
WR_SECT => rw_byte_wr_sect,
SECTOR_OUT => rw_byte_sector_out,
RAM_DI => rw_byte_ram_di,
DATA_OUT => rw_byte_data_out,
TRACK_OUT => rw_byte_track_out,
ADDR_OUT => rw_byte_addr_out
);
rw_byte_side_in <= rd_fat_side when rd_fat_bsy = '1' else wr_fat_side;
rw_byte_sector_in <= rd_fat_sector when rd_fat_bsy = '1' else wr_fat_sector;
rw_byte_track_in <= rd_fat_track when rd_fat_bsy = '1' else wr_fat_track;
rw_byte_rd_byte <= rd_fat_rd_byte or wr_fat_rd_byte;
rw_byte_wr_byte <= wr_fat_wr_byte;
rw_byte_addr_in <= rd_fat_ram_addr when rd_fat_bsy = '1' else wr_fat_ram_addr;
c2 : read_fat port map(
EN => fdd_rdy,
MCLK => MCLK,
BSY => rd_fat_bsy,
ENTRY => i2c_man_fat_entry,
RD => rd_fat_rd,
DATA_IN => rw_byte_data_out,
FAT_OUT => rd_fat_fat_out,
RAM_ADDR => rd_fat_ram_addr,
SECTOR => rd_fat_sector,
SIDE => rd_fat_side,
TRACK => rd_fat_track,
RD_BYTE => rd_fat_rd_byte,
RW_BSY => rw_byte_bsy
);
c3 : write_fat port map(
EN => fdd_rdy,
MCLK => MCLK,
WR => wr_fat_wr,
RW_BSY => rw_byte_bsy,
DATA_IN => rw_byte_data_out,
ENTRY => i2c_man_fat_entry,
FAT_VALUE => i2c_man_fat_value_out,
RD_BYTE => wr_fat_rd_byte,
WR_BYTE => wr_fat_wr_byte,
SIDE => wr_fat_side,
BSY => wr_fat_bsy,
SECTOR => wr_fat_sector,
TRACK => wr_fat_track,
DATA_OUT => rw_byte_data_in,
RAM_ADDR => wr_fat_ram_addr
);
c4 : i2c_manager port map(
RST => RST,
MCLK => MCLK,
RAM_DO => fdd_data_out,
RDY => fdd_rdy,
BSY => fdd_bsy,
CRC_ERROR => fdd_crc_error,
SEEK_ERROR => fdd_seek_error,
WP_ERROR => fdd_wp_error,
FAT_VALUE_IN => rd_fat_fat_out,
DIR_OFFSET => sd_offset,
I2C_ADDR => I2C_ADDR,
TRACK => i2c_man_track,
SIDE => i2c_man_side,
WR_SECT => i2c_man_wr_sect,
RD_SECT => i2c_man_rd_sect,
SECTOR => i2c_man_sector,
FAT_VALUE_OUT => i2c_man_fat_value_out,
FAT_ENTRY => i2c_man_fat_entry,
DIR_ENTRY => i2c_man_dir_entry,
MEM_WE => i2c_man_ram_we,
RAM_CLK => i2c_man_ram_clk,
RD_FAT => rd_fat_rd,
WR_FAT => wr_fat_wr,
SET_DIR => i2c_man_set_dir,
WR_DIR => i2c_man_wr_dir,
RAM_DI => i2c_man_ram_di,
MEM_ADDR => i2c_man_ram_addr,
SCL => SCL,
SDA => SDA
);
c5 : set_directory port map(
FDD_RDY => fdd_rdy,
MCLK => MCLK,
FDD_BSY => fdd_bsy,
RAM_WE => sd_ram_we,
ENTRY => i2c_man_dir_entry,
SET => i2c_man_set_dir,
WR_DIR => i2c_man_wr_dir,
SET_BSY => sd_bsy,
TRACK => sd_track,
SIDE => sd_side,
SECTOR => sd_sector,
OFFSET => sd_offset,
WR_SECT => sd_wr_sect,
RD_SECT => sd_rd_sect
);
end idc_top_arch;
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