flipflop.vhd

--------------------------------------------------------------------------

-- FILENAME : flipflop.vhd

--

-- A single D type flip flop.  Two of these flip flops are used by the

-- synchronizer module.

--

-- AUTHOR       : Craig Dunn

-- DATE STARTED : 8 December 2003

-- TAB SETTING  : 4

-- CLEAR        : Async (active low)

-- KNOWN BUGS   : None

-- VERSION      : 1.0

--

-- All of the design and code in this module is my own work.  No design or

-- code has been borrowed or copied from any source.

--------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_ARITH.all;

use IEEE.STD_LOGIC_UNSIGNED.all;



entity flipflop is

    port ( D      : in  std_logic;

           CLK    : in  std_logic;          

           CLR    : in  std_logic;

           Q      : out std_logic

         );

end flipflop;



architecture flipflop_arch of flipflop is

begin



   main : process(CLK, CLR)

   begin

      if CLR = '0' then

         Q <= '0';

      elsif rising_edge(CLK) then

         Q <= D;

      end if;

   end process;



end flipflop_arch;