 | dpll.vhd
--------------------------------------------------------------------------
-- FILENAME : dpll.vhd
--
-- The Digital Phase Locked Loop. Generates a 1MHz clock which is locked
-- the Basic MFM signal.
--
-- See the project report for a detailed description.
--
-- AUTHOR : Craig Dunn
-- DATE STARTED : 15 December 2003
-- TAB SETTING : 4
-- RESET : Async (active low)
-- CLOCK : 4MHz (clock dependent)
-- KNOWN BUGS : None
-- VERSION : 1.0
--
-- All of the design and code in this module is my own work. No design or
-- code has been borrowed or copied from any source.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity dpll is
port ( RST : in std_logic;
CLK_4MHZ : in std_logic;
BASIC_MFM : in std_logic;
DPLL_CLK : out std_logic
);
end dpll;
architecture dpll_arch of dpll is
type dpll_type is ( SA, SB, SC, SD, SE );
signal dpll_state : dpll_type;
signal a_mfm : std_logic;
signal d_mfm : std_logic;
begin
main : process(RST, CLK_4MHZ)
begin
if RST = '0' then
dpll_state <= SA;
d_mfm <= '0';
elsif rising_edge(CLK_4MHZ) then
case dpll_state is
---------------------------------------------------------------
when SA =>
DPLL_CLK <= '1';
if d_mfm = BASIC_MFM then
dpll_state <= SB;
else
dpll_state <= SE;
end if;
a_mfm <= BASIC_MFM;
---------------------------------------------------------------
when SB =>
DPLL_CLK <= '1';
if a_mfm = BASIC_MFM then
dpll_state <= SC;
else
dpll_state <= SD;
end if;
---------------------------------------------------------------
when SC =>
DPLL_CLK <= '0';
dpll_state <= SD;
---------------------------------------------------------------
when SD =>
DPLL_CLK <= '0';
d_mfm <= BASIC_MFM;
dpll_state <= SA;
---------------------------------------------------------------
when SE =>
dpll_state <= SB;
when others =>
null;
end case;
end if;
end process main;
end dpll_arch;
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