crc.vhd

--------------------------------------------------------------------------

-- FILENAME : crc.vhd

--

-- Performs a parallel CCITT CRC on DATA_IN.  The properties of the CRC 

-- are:

--

--    Poly       : X^16 + X^12 + X^5 + 1

--    Reflecting : None

--    Final XOR  : None

--    Width      : 16 bits

--

-- It's upto the module using this CRC to initialise it to 0xFFFF, as 

-- used by the floppy disk.

--

-- This design is based on the standard serial design, but I have 

-- converted it to parallel.  See the final report to see how this was

-- done.

--

-- AUTHOR       : Craig Dunn

-- DATE STARTED : 7 Februaury 2004

-- TAB SETTING  : 4

-- RESET        : None

-- CLOCK        : None

-- KNOWN BUGS   : None

-- VERSION      : 1.0

--

-- All of the design and code in this module is my own work.  No design or

-- code has been borrowed or copied from any source.

--------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity crc is

    port ( DATA_IN   : in std_logic_vector(7 downto 0);

           CRC_IN    : in std_logic_vector(15 downto 0);

           CRC_OUT   : out std_logic_vector(15 downto 0)

         );

end crc;



architecture crc_arch of crc is

begin



   CRC_OUT(0)  <= CRC_IN(12) xor CRC_IN(8)  xor DATA_IN(4) xor DATA_IN(0);

   CRC_OUT(1)  <= CRC_IN(13) xor CRC_IN(9)  xor DATA_IN(5) xor DATA_IN(1);

   CRC_OUT(2)  <= CRC_IN(14) xor CRC_IN(10) xor DATA_IN(6) xor DATA_IN(2);

   CRC_OUT(3)  <= CRC_IN(15) xor CRC_IN(11) xor DATA_IN(7) xor DATA_IN(3);

   CRC_OUT(4)  <= CRC_IN(12) xor DATA_IN(4);

   CRC_OUT(5)  <= CRC_IN(13) xor DATA_IN(5) xor CRC_IN(8)  xor CRC_IN(12) xor DATA_IN(4) xor DATA_IN(0);

   CRC_OUT(6)  <= CRC_IN(14) xor DATA_IN(6) xor CRC_IN(9)  xor CRC_IN(13) xor DATA_IN(5) xor DATA_IN(1);

   CRC_OUT(7)  <= CRC_IN(15) xor DATA_IN(7) xor CRC_IN(10) xor CRC_IN(14) xor DATA_IN(6) xor DATA_IN(2);

   CRC_OUT(8)  <= CRC_IN(15) xor CRC_IN(11) xor DATA_IN(7) xor CRC_IN(0)  xor DATA_IN(3);

   CRC_OUT(9)  <= CRC_IN(12) xor CRC_IN(1)  xor DATA_IN(4);

   CRC_OUT(10) <= CRC_IN(13) xor CRC_IN(2)  xor DATA_IN(5);

   CRC_OUT(11) <= CRC_IN(14) xor CRC_IN(3)  xor DATA_IN(6);

   CRC_OUT(12) <= CRC_IN(15) xor CRC_IN(4)  xor DATA_IN(7) xor CRC_IN(8) xor CRC_IN(12) xor DATA_IN(4) xor DATA_IN(0);

   CRC_OUT(13) <= CRC_IN(13) xor CRC_IN(9)  xor DATA_IN(5) xor CRC_IN(5) xor DATA_IN(1);

   CRC_OUT(14) <= CRC_IN(14) xor CRC_IN(10) xor DATA_IN(6) xor CRC_IN(6) xor DATA_IN(2);

   CRC_OUT(15) <= CRC_IN(15) xor CRC_IN(11) xor DATA_IN(7) xor CRC_IN(7) xor DATA_IN(3);



end crc_arch;