*

clock_divider.vhd


--------------------------------------------------------------------------

-- FILENAME : clock_divider.vhd
--
-- Divide the input MCLK by 4 to produce a 4MHz output. The 4MHz output
-- is used to clock the DPLL.
--
-- AUTHOR : Craig Dunn
-- DATE STARTED : 15 December 2003
-- TAB SETTING : 4
-- RESET : Async (active low)
-- CLOCK : 32MHz
-- KNOWN BUGS : None
-- VERSION : 1.0
--
-- All of the design and code in this module is my own work. No design or
-- code has been borrowed or copied from any source.
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_divider is
port ( RST : in std_logic;
MCLK : in std_logic;
CLK_4MHZ : out std_logic
);
end clock_divider;

architecture clock_divider_arch of clock_divider is
signal clock : std_logic;
signal edge_count : integer range 0 to 3;
begin

CLK_4MHZ <= clock;

main : process(RST, MCLK)
begin
if RST = '0' then
clock <= '1';
edge_count <= 0;
elsif rising_edge(MCLK) then
if edge_count = 3 then
clock <= not clock;
edge_count <= 0;
else
edge_count <= edge_count + 1;
end if;
end if;
end process main;


end clock_divider_arch;


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